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Accommodating workload diversity in chip multiprocessors via

With the rapid development of computer industry, the number of applications has been growing rapidly.

Leveraging optical technology in bus-based multicore design. on Computer Architecture (ISCA), Tel Aviv, Israel, June 2013 [PDF] J. Overcoming single-thread performance hurdles in the Core Fusion reconfigurable multicore architecture. An efficient all-optical on-chip interconnect based on oblivious routing. on Architectural Support for Programming Languages and Operating Systems, Pittsburgh, PA, March 2010 [PDF] R. We demonstrate that Sim-EA exhibits large elasticities over 26 benchmarks of SPEC CPU2000, enabling Sim-EA to reduce the average energy-delay product (EDP) by 31.14% of a fixed baseline architecture. SWAP: Effective fine-grain management of shared last-level caches with minimum hardware support. Leveraging optical technology in future bus-based chip multiprocessors. Cherry-MP: Correctly integrating checkpointed early resource recycling in chip multiprocessors. By employing reconfigurable architecture components (instruction set, branch predictor, data path, memory hierarchy, concurrency, status & control, and so on), the EA can achieve considerable elasticities on each application, which enables the EA to meet the performance or power requirements associated with each application scenario.We validate the effectiveness of the EA on a prototype implementation called Sim-EA.

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