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Accommodating workload diversity in chip multiprocessors via
An efficient all-optical on-chip interconnect based on oblivious routing.
on Architectural Support for Programming Languages and Operating Systems, Pittsburgh, PA, March 2010 [PDF] R.
In IEEE Micro Top Picks from Computer Architecture Conferences, Jan.-Feb.
Leveraging optical technology in bus-based multicore design.
on Field-Programmable Custom Computing Machines (FCCM), Boston, MA, May 2014 [PDF] J.
Understanding and Mitigating Refresh Overheads in High-Density DDR4 DRAM Systems.
This trend raises the following question: how to design processors that best suit millions of application scenarios?
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It is impractical to design a dedicated processor for each single application scenario.
Coordinated management of multiple resources in chip multiprocessors: A machine learning approach.
Scavenger: A new last level cache architecture with global block priority.
on Computer Architecture (ISCA), Tel Aviv, Israel, June 2013 [PDF] J.
Overcoming single-thread performance hurdles in the Core Fusion reconfigurable multicore architecture.